The testing of manufactured electronics has long been an area of focus in the electronics industry. The importance of testing in the manufacture of semiconductor integrated circuit (IC) chips has escalated because of ever increasing process complexity and device density. A problem area in IC chip manufacturing is achieving the dwindling feature sizes necessary to accomplish greater device densities. The meaning of the term "devices" here comprises all the desirable electrical circuit elements to which those skilled in the integrated circuit arts seek to achieve on their chips. For example, active elements like transistors and diodes, passive elements such as capacitors and resistors, or the substrates, metal wires and insulators used to connect the above into circuits. These devices area built up from the formation of three-dimensional features which have both horizontal and vertical dimensions. Examples of device features would be bases, emitters, collectors, gates, sources, drains, contacts, trenches, reach-throughs, buried straps, local interconnects, first level metal, inter-level dielectric, stud, via, and so on as understood by those skilled in the art. The features are made by applying design patterns to sequential layers. The design patterns control the horizontal dimensions of a feature as defined by the mask art; while the layers control the vertical dimensions of a feature by way of carefully defined process recipes.
As lithography advances allow device features to shrink their dimensions horizontally, control of the attendant vertical dimensions becomes increasingly difficult and important. While test structures for in-line monitoring of horizontal process parametrics has long been the norm, the same has not been true for vertical process parametrics, particularly for in-line process monitoring. There are a number of techniques used for controlling the horizontal dimensions and profile of integrated circuit devices. An important example is optical metrology, where optical measurement techniques involving microscopes, SEM's, TEM's and the like, measure minimum size features found on comb structures included in the mask art. These structures are placed in an area of open chip or wafer real estate. This is typically in the kerf area of the wafer but may also include partial chip site locations, any open area within the chip, or any other open and available real estate on the wafer. These comb structures are typified by ordered columns of fingers. The fingers are at a minimum width and spaced from one another at the minimum space as allowed by the lithography technology employed in building that chip. Optical or electron microscopy measurement of these combs, as exposed on a wafer, allows timely feedback for the control of horizontal feature dimensions. The advantage provided here is that this measurement technique is non-invasive and non-destructive of the wafer and chips. It allows measurement to be made in-line, along side of (or even in) the processing tool which created the horizontal feature dimension. This allows process and exposure variations to be compensated for in a timely manner. As a result, less product gets mis-processed and identified as scrap. Vertical parametric control, however, must rely upon less desirable methodologies.
The measurement for parametric control of vertical features generally relies upon chip cross-sectioning and reverse engineering techniques. A sampling plan is implemented. A sacrificial wafer is selected from a given wafer lot each time the lot passes through a selected process step in the manufacturing line. The sacrificial wafer is cut apart and the edge polished to expose a vertical profile which can be measured with SEM or TEM equipment. This is a time-consuming process performed off-line in another facility. Meanwhile, the wafer lot continues through the processing line. So, if a wafer lot was mis-processed, additional cost is incurred processing a bad lot. Even when there is no mis-processing, a wafer of product is lost to measurement.
There are various combinational techniques which can be used to avoid chip cross-sectioning. As an example, on levels which are conductive, measurements taken of sheet resistance structures can be used in combination with the horizontal parametrics measurements to infer the vertical thickness achieved for that level on that wafer. However, when the result is not as expected, it is very difficult to determine the exact type of mis-processing. A common problem involves the underlying topography, namely, variance from substantial planarity as needed in the processing of subsequent layers. It is unknown whether the unexpected increase in sheet resistance results from too thin a layer of material as deposited, or because there is an underlying topography disruption along the path of the sheet resistance structure. Such a topography disruption can cause localized thinning in the structure and thus result in an increase to the resistance measurement. Further, some topography disruptions will cause shorts to occur instead, thus resulting in clearly erroneous results, without indication of what might be wrong. So again, cross-sectioning of a sacrificial wafer must be relied upon to discover the mis-processing problem. This is a problem particularly for a process like Damascene which requires substantial planarity from the underlying topography.
Damascene is a process used to provide the metal interconnects on IC chips. An exemplary example of a Damascene method is described in U.S. Pat. No. 4,789,648 to Chow et al., the disclosure of which is incorporated by reference herein. In its essence, producing IC wiring interconnect with Damascene involves first providing a planarized layer of insulator. Second, a channel is etched in the planarized layer where interconnect wires are desired. Third, metal is deposited to cover over and fill the channels. Finally, excess metal which overlies the insulator is removed with a chemical mechanical polish technique to isolate the metal in the channels and coplanarize the surface. An exemplary example of chemical mechanical polishing is described in U.S. Pat. No. 4,944,836 to Beyer et al., the disclosure of which is incorporated by reference herein.
There are problems which can manifest themselves in a Damascene-like process. One, as discussed above, is where topography problems cause the surface of the insulator to vary from the essential coplanarity and, as such, not all deposited metal gets polished off by the chemical mechanical polishing. Another problem is when a scratch develops on the surface of the insulator prior to the metal deposition. This may be the result of simple wafer mishandling or result from particulate contamination in the chemical mechanical polishing step. Another problem found with a Damascene process is where an over-polishing condition results from a variation in pattern factor of the underlying metal line widths or other topography found across the chip.
The pattern factor is the ratio of metal to total (insulator plus metal) area for a given region of the chip, as view from above, where area is in the plane of the chip surface. It is expressed as a percentage of metal area divided by the total chip area in the chip region that includes the metal shapes of interest. Different pattern factors result as a consequence of the variation in metal line widths and line densities found across a chip site. Metal lines used as signal carriers are typically at the minimum feature size width allowed for that level of metal and for a given process technology. Metal lines used to supply circuit power from the voltage supplies are made wide by design. This results from a need to minimize any voltage drop seen between the power supply and the destination circuit. This need is best achieved by keeping the metal resistance as low as possible, which in turn, means making the power supply metal line widths as wide as possible.
FIGS. 1A-E depict how topography variation may affect a Damascene process. In FIG. 1A, an insulator 10 has been pattern etched and covered with deposited metal 11. This deposited metal is chemically mechanically polished back until narrow wires 12 and wide wires 13 are formed as depicted in FIG. 1B. Note that dishing (e.g. a concave or non-coplanar area) has formed on wide wires 13. This result is from a local over-polishing condition caused by the local compliance of the polish pad and the difference in polish rates for metals and insulators. In FIG. 1C, a conformal insulator 14 has been applied on the wafer. Note that the conformal insulator has replicated the dishing of wide lines 13 to the surface. Etching of channels 15 is shown in FIG. 1D as preparation to creating second level metal wires. In FIG. 1E, the channels 15 have been filled with deposited metal and this metal has been polished back to form second level wires 16 and 17. However, wires 17 were formed over the topographical dishing caused from over-polishing of wide wires 13. As a result, the metal is not entirely removed from between the wires 17 as was desired and a metal puddle 18 is formed which shorts the wires 17 together. While the example used in FIGS. 1A-E depicts an over-polish topography problem, there are other topography perturbations which may cause similar results. These include but are not necessarily limited to topography problems from scratching, particle contamination, mishandling and mis-processing in fabrication. These topography deviations can either be negative or positive (i.e. concave or convex), leading to shorts or opens, respectively, for metal lines on subsequent wiring levels.
Therefore, there exists a demand for chip testing in a manufacturing environment which is both timely, and yet provides an improved quality and quantity of test results. There also exists a demand for vertical parametric in-line test structures. Also, there is a demand for on-wafer topography monitors which will indicate topography problems in the fabrication of IC wafers. Lastly, there is a demand for a wafer test structure to monitor dishing resulting from scratches and over-polish conditions. Thus, it would be desirable to provide a means for satisfying such demands and solving the aforesaid and other deficiencies and disadvantages.